1. Field of Invention
The present invention relates to a chip scale package structure and a manufacturing method of the chip scale package structure.
2. Description of Related Art
General chip scale package structures used in microelectromechanical systems (MEMS) are manufactured by quad flat no leads (QFN). Chips have pads and are electrically connected to external circuit contacts by wire-bonded to the pads. Thereafter, encapsulating glue is applied to cover the wire-bonded chips and external circuit contacts.
However, the thickness and the width of the chip scale package structure are limited by the available wiring area of the bonding wire, so as to difficultly reduce the thickness and the width, and thus the size of the chip scale package structure. Moreover, the chip scale package structure cannot directly be shipped out in wafer level package, and cannot be shipped out as a chip scale package without further manufacturing processes after being diced.
Furthermore, the chip scale package structure is absent from electromagnetic interference (EMI) preventing element, and is vulnerable to the disturbances of other electronic components.